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NXP Semiconductors /LPC5410x /MAILBOX /IRQ0CLR

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Interpret as IRQ0CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0INTREQCLR

Description

Clear bits in IRQ0

Fields

INTREQCLR

Writing 1 clears the corresponding bit in the IRQ0 register.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data